A laterally diffused metal oxide semiconductor (LDMOS) field effect transistor (FET) is a transistor having a drift region between a gate and a drain region in order to avoid a high electric field at a drain junction, i.e., at the p-n junction between a body and the drain region. An LDMOS device is typically employed in high voltage power applications involving voltages in the range from about 5 V to about 200 V, which is applied across the drain region and the source region. A substantial fraction of the high voltage may be consumed within the drift region in the LDMOS device so that the electric field generated across the gate dielectric does not cause breakdown of the gate dielectric.
Voltage breakdown and hot carrier shifting can occur in various locations within high voltage devices, such as high voltage LDMOS devices. These mechanisms are driven by high electric fields, high current densities, and the interaction of the two. High electric fields mainly occur in at p-n junctions and locations of sharp corners in the structure of a high voltage device.
A field plate comprised of gate oxide and polysilicon is often used to reduce the electric field in the drift region. However, the field plate introduces an additional discontinuity in the device at the drain edge of the field plate. To enhance the action of the field plate and provide improved breakdown voltage margin at the drain, a step oxide configuration is sometimes used. In a step oxide configuration there, is a sharp vertical discontinuity (i.e., a step) at the transition point between a first region of a gate oxide having a first thickness and a second region of the gate oxide having a second thickness. The sharp discontinuity results in a large electric field that is in the current path which can drive hot carrier degradation as well as voltage breakdown.